• 专利附录
  • 专利说明
  • 权利要求
  • 类似技术
  • 同族专利
  • 引用文献
  • 法律状态
  • 优先权
    • 专利摘要:
      INTEGRATED OPTICAL RECEIVER ARCHITECTURE FOR HIGH SPEED OPTICAL I / O APPLICATIONS.The present invention addresses an integrated optical receiver architecture that can be used to couple light between a multi-mode fiber (MMF) and a silicon chip that includes integration of a silicon demultiplexer and a high-speed Ge photodetector. The proposed architecture can be used for both optical links based on wavelength division (WDM) and parallel multiplexing with a data rate of 25 Gb / s and higher.
    公开号:BR112012016161A2
    申请号:R112012016161-0
    申请日:2010-12-10
    公开日:2020-09-01
    发明作者:Ansheng Liu
    申请人:Intel Corporation；
    IPC主号:
    专利说明:

    F "~.
    "TNTEGRATED OPTICAL RECEIVER ARCHITECTURE FOR HIGH SPEED OPTICAL I / O APPLICATIONS". and
    FIELD OF THE INVENTION Modalities of the present invention are directed to 5 optical receivers and, more particularly, to optical receivers integrated with built-in funnels (tapers) for improved fiber alignment tolerances.
    HISTORICAL INFORMATION Efficient light coupling between an optical fiber 10 and a silicon waveguide is highly desired for the silicon based ion device and circuit applications.
    Due to the high contrast index of refraction of silicon waveguide systems, obtaining a good silicon fiber waveguide coupling can be challenging. 15 In optical communication, information is transmitted through an optical carrier, whose frequency is typically in the visible or near infrared region of the electromagnetic spectrum. A carrier with such a high frequency is sometimes referred to as an optical signal, an optical carrier, or a light signal. A typical optical communication network includes several optical fibers, each of which can include several channels. A channel is a specific frequency band of an electromagnetic signal, and is sometimes referred to as a wavelength. 25 Technological advances today include optical communication at the integrated circuit (or chip) level. This is because integrated circuits have several advantages that are attractive in computer systems. Sometimes designers connect an optical signal (light) between two chips, between one. chip and 30 a die (in the system), or between two matrices. This is traditionally accomplished using an optical fiber to couple light between waveguides in the arrays or chips.
    A limitation of using fiber optics to couple light between waveguides in arrays or chips is that this method of coupling tends to be inefficient. One reason is because of the difference in physical size between the optical fiber and a guide
    2/7 .
    typical wave on a chip or matrix. The optical fiber tends to be much larger than the waveguide. Because of the size difference the coupling efficiency of the optical signal is poor. That is, the larger diameter fiber optic light does not fit well within the small waveguide. The result may be that the light levels received are so low that the individual bits in the data stream in the optical signal become indistinguishable. When this occurs, the receiving component may not be able to retrieve information from the data stream. 10 The coupling efficiency can be improved by attaching lenses to the optical fiber or by placing a lens between the optical fiber and the waveguide to focus the optical signal on a waveguide. However, coupling efficiency is only regular using lenses. Other methods of coupling result in efficiencies that are also regular at best.
    This limitation also comes with another challenge, such as efficient coupling of the optical mode supported by the largest optical fiber to the smallest optical mode supported by the 20-wave guide. The mode is the Optical energy cross section distribution (Gaussian distribution) and is defined by the size of your waveguide (optical fiber, planar waveguide) and the wavelength of the light. There is a large optical mode in the higher optical fiber and a smaller optical mode in the smaller waveguide. 25 Also, the coupling of an optical fiber with small waveguides in the matrix requires very precise alignment. This is typically accomplished with specialized precision manual alignment procedures. Such specialized alignment procedures are typically very expensive and 30 limit practical volumes.
    Today, there is a global problem that exists for a low cost multi-mode fiber optic receiver (FMF) for high speed applications. To achieve high speed, for example, 25 Gb / s and greater in the uirt 35 photodetector (PD) operation, the active area of the detector generally needs to be small. However, in order to efficiently couple the mqF light, a chip based on a sewiconductor waveguide containing photodetectors and, eventually, an optical multi-detector, a large waveguide size is used for the large misalignment tolerance. necessary for low-cost passive alignment.
    BRIEF DESCRIPTION OF THE DRAWINGS The background and a better understanding of the present invention may become evident from the following detailed description of exemplary arrangements and modalities and from the claims, when read in connection with the artifacts, 10 all forming a part of the description. of the present invention.
    While the preceding and the following written and illustrated description concentrate on describing exemplary arrangements and modalities for the invention, it should be clearly understood that the same are as a form of illustration and example only, and the invention is not limited to them.
    Figure 1 is a side view of an integrated optical receiver in accordance with an embodiment of the invention; Figure 2 is a view of the silicon substrate 20 on insulator (SOI) to form the optical receiver shown in Figure 1; Figure 3 is a side view of the SOI wafer illustrating the etching of the funnel; Figure Ll is a side view of the SOI 25 wafer illustrating the engraving of the V-slot for the mirror; Figure 5 is a side view of the SOI wafer illustrating the deposition of an odile layer for the total internal reflection mirror; Figure 6 is a side view of the teni SOI wafer 30 a silicon wafer attached at the top; Figure 7 is a side view of the SOI shown in Figure 6 facing the additional silicon photonic processing of the photodetector (PD) and optional grid (grating), as shown in Figure 1; 35 Figure 8 is a graph illustrating the loss of optical modeling for the V-slot mirror structure of the integrated optical receiver under single mode conditions; and
    . Q Figure 9 is a graph illustrating the loss of: W optical modeling for the V-slot mirror structure of the integrated optical receiver under multi-mode conditions.
    DETAILED DESCRIPTION 5 An integrated optical receiver architecture aimed at coupling light between a multi-mode fiber (MMF) and silicon chip is described, as well as the integration of a silicon demultiplexer and a high-speed photodetector. The proposed architecture can be used for both optical links 10 based on multiplexing by wave length division (WDM) and parallel with a data rate of 25 Gb / s, and higher.
    Reference to a long description of "a modality" or "modality" means that a particular feature, structure, or feature described in connection with the modality is included in at least one embodiment of the present invention. Thus, the appearances of the phrases "in one modality" or "in modality" in various places throughout this descriptive report are not necessarily all referring to the same modality. Aderaais, the particular characteristics, structures or particularities can be combined in any suitable way, in one or more modalities.
    Referring now to Figure 1, the optical receiver is shown according to a modality of the invention. Optical receiver 100 comprises a silicon wafer portion 102 25 in which a total internal reflection mirror (TIR) structure 104 is located. A waveguide portion 106 comprises a wide end to which the light from a fiber, such as a multi-mode optical fiber 108, can be fed. The light can be echoed through a lens 110. The guide wire 106 30 comprises a funnel 112, on which the waveguide narrows from the bottom. The TIR structure comprises a wedge 114 which has a reflective surface to direct light, moving parallel to substrate 102, is reflected upwards to a high-speed photodetector 116 as indicated by the arrows. An optional silicon demultiplexer 118 can also be manufactured on waveguide 106, as shown. For example, the demultiplexer may comprise a diffraction network, such as the illustrated etched Echelle network. The recorded Echelle network may be capable of demultiplexing both single-beam and multi-mode beams.
    This integrated silicon chip shown in Figure 1 can be manufactured on a silicon substrate on insulator (SOI). For parallel link applications, the demultiplexer may not be included. The inlet of the silicon funnel 112 has a height of 20 to 30 µin at the wide end for efficient coupling between the MMF 108 and the chip with a plastic wire 110. The final height of the waveguide 106 after the funnel is - 10 µrri. The funnel can be manufactured, for example, using grayscale technology as described in "Optics Express", vol. 11, n '. 26, 3555-3561 (2003), hereby incorporated by reference.
    Note that the size of the final waveguide should probably not be small, due to the possible modal filtering effect (optical loss} for a multi-mode beam emitted from IIMF 108. The TIR 104 reflection mirror portion is used for coupling the light from the waveguide vertically to a high-speed germanium (Ge) detector 116 grown on top of the silicon, the technique of making such a PD of Ge 116 is well established. tapered wave incident on the Ge PD can be reflected from "the metal contact at the top of the Ge layer in the detector, the double optical path is reached in the active Ge region. This leads to greater quantum efficiency with a film of Ge reduttjra (thinner) for a higher speed The estimated speed of the detector with a Ge thickness of ~ 1.5 µm is> 20 Ghz, good for 25 Gb / s applications.
    Figures 2 to 7 illustrate the manufacturing steps of the integrated silicon receiver chip. proposed according to one modality. Referring now to Figure 2, Lútl silicon wafer on insulator (SOI) comprises a silicon substrate, a buried oxide layer (BOX) 202 and a silicon treatment layer 204 in the BOX 202 layer. The Si 204 layer can be approximately 20 to 30 µm thick. This stroke thickness can be different for different applications. A layer
    € of rigid mask (HM) of protective oxide 206 may be on top of the Si 204 layer. In Figure 3, the funnel portion of the waveguide in Figure 1 is engraved through the EM 206 layer and up to 5 etched through the Si 204 layer at a recording depth of approximately 10 µrn. The engraved portion can generally be rectangular at one end and tapered at the other. In Figure 4, an errt V 400 slot can be further engraved from the Si 204 layer for later formation of the wedge mirror 114 10 shown in Figure 1_ The V 400 slot can be engraved, for example, with a wet recording of potassium hydroxide (KOH). The slot engraving on the V 400 can, in some modalities, reach the buried oxide (BOX) 202 or leave a thin layer of silicon (0.5 to 1 µrn) for the subsequent growth of Ge.
    In Figure 5, the engraved trenches are filled with oxide 500 followed by chemical mechanical pIanization (CMP). The oxide comprises the total internal reflection mirror (TIR) shown in Figure 1. 20 In Figure 6 c) planarized wafer will be linked wafer with a separate silicon wafer 102. After connecting the wafer, the original treatment wafer 200 of the wafer SOI is going to be removed. As shown in Figure 7, all equipment can be turned over. Removing treatment wafer 200 creates a new wafer with BOX 202 25 as a rigid mask. The BOX layer of rigid mask (HM} 202 can be used for the additional process of Echelle 118 mesh and photodetector (PD) of Ge as shown in Figure 1, whose processing techniques are well known in the art. to Figures 8 and 9, the optical loss of the erri V slot mirror structure is modeled under single and multiple mode launching conditions, respectively. Cow an 54.7 ° V slot angle, the case) of Figure 8 shows that there is almost no optical loss. As shown in Figure 9, for the case of multiple 35 modes with 0 to 5 emission modes there is a drop of only -0.36 d8. It should also be noted that even if a non-etched μm silicon layer corrt to the V-slot mirror, the optical loss is still small. So most of the light is reflected in the mirror plane and directed towards the DP 116.
    The above description of the illustrated modalities of the invention, including what is described in the Summary, is not intended to be exhaustive or to limit the invention to the precise foregoing described. Although specific embodiments and examples of the invention have been described for illustrative purposes, several equivalent details are possible within the scope of the invention, as those skilled in the relevant art will recognize. Such modifications can be carried out in the invention, in the light of the detailed description. The terms used in the following claims should not be interpreted to limit the invention to the specific modalities described in the report and the claims. On the contrary, the scope of the invention must be determined entirely by the following claims, which must be interpreted in accordance with the established doctrines of the interpretation of claims.
    权利要求:
    Claims (20)
    [1]
    1. Equipment characterized by comprising: a silicon substrate; a total internal reflection mirror structure (TIR) on the silicon substrate, the mirror structure TIR comprising a first portion and a second portion thicker than the first portion; a funneling portion transiting between the first portion and the second portion of the TIR mirror structure; a V-groove wedge integral with the second portion of the TIR mirror structure; a guide to the top of the TIR mirror structure; and a photodetector (PD) manufactured on the wave guide next to the groove wedge erri V.
    [2]
    2. Equipment according to claim 1, characterized by the fact that it additionally comprises a demultiplexer formed on the waveguide in front of the V-groove wedge.
    [3]
    3. Equipment, according to claim 1, characterized by the fact that the fat-detector comprises a high-speed Germanium photodetector.
    [4]
    4. Equipment, according to claim 2, characterized by the fact that the demultiplexer comprises a diffraction network.
    [5]
    5. Equipment according to claim 4, characterized by the fact that the diffraction network comprises a recorded Echelle network that is capable of demultiplexing both single-mode and multi-mode beams.
    [6]
    6. Equipment according to claim 1, characterized by the fact that the waveguide comprises an entry end approximately 20 to 30 µm thick.
    [7]
    7. Equipment, according to claim 6, characterized by the fact that the thickness after the funnel is about 10 µm thick.
    [8]
    8. Method for manufacturing an integrated optical receiver characterized by comprising:
    Offer a silicon wafer on insulator (SOI) - comprising a silicon treatment layer, a buried oxide layer (BOX), a silicon waveguide layer and a rigid mask oxide layer (HM); 5 etching a funnel into the HM layer and the silicon waveguide layer; etching a V-groove across a portion of the silicon layer; fill the funnel and the groove in V with oxide 10 to form a mirror structure of total internal reflection (TIR); planarize the TIR mirror structure; glue a silicon wafer to the TIR mirror structure; 15 flip the SOT wafer; removing the silicon treatment layer; and manufacture a high-speed photodetector (PD) unit on the V-slot.
    [9]
    Method according to claim 8, 20 characterized by the fact that it additionally comprises making a demultiplexer in the silicon waveguide layer.
    [10]
    10. Method according to claim 8, characterized by the fact that the photodetector comprises a germline photodetector (Ge).
    [11]
    11. Method according to claim 9, characterized by the fact that the demultiplexer comprises a diffraction grating.
    [12]
    12. Method according to claim 11, characterized in that the diffraction network comprises a recorded Echelle network capable of demultiplexing both beams in a single and multiple modes.
    [13]
    13. Method according to claim 8, characterized in that the funnel comprises a wide end of approximately 20 to 30 µin thick and a narrow end of approximately 10 µm thick.
    *.
    .
    3/3%,
    [14]
    14. Method, according to claim 8, characterized by the fact that the V-slot is engraved for the BOX layer.
    [15]
    15. Method, according to claim 8, · 5 characterized by the fact that the V-slot is engraved in a short form on the BOX layer.
    [16]
    16. Integrated optical receiver system characterized by comprising: a silicon substrate; 10 a total internal reflection mirror (TIR) structure on the silicon substrate; a silicon waveguide on the TIR mirror structure, the silicon waveguide having a wide entry end that tapers to a narrow straight end, the entry end to receive light from a multi-mode fiber; a photodetector manufactured on a portion of the narrower end of the waveguide; and a wedge portion on the mirror structure 20 TIR under the photodetector to reflect the light up to the photodetector.
    [17]
    17. System according to claim 16, characterized by the fact that it additionally comprises a lens between the multi-mode fiber and the inlet end of the silicon waveguide. 25 i8.
    [18]
    System according to claim 16, characterized in that it additionally comprises a demultiplexer formed on the waveguide before the wedge.
    [19]
    19. System, according to claim 16, characterized by the Eato that the photodetector is a photodetector of 30 germanium.
    [20]
    20. System, according to claim 18, characterized by the fact that the multiplexer is an Echelle network.
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    法律状态:
    2020-09-15| B06U| Preliminary requirement: requests with searches performed by other patent offices: procedure suspended [chapter 6.21 patent gazette]|
    2021-10-13| B06A| Patent application procedure suspended [chapter 6.1 patent gazette]|
    2021-11-23| B350| Update of information on the portal [chapter 15.35 patent gazette]|
    2021-12-28| B09A| Decision: intention to grant [chapter 9.1 patent gazette]|
    优先权:
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    US12/651,314|2009-12-31|
    US12/651,314|US8319237B2|2009-12-31|2009-12-31|Integrated optical receiver architecture for high speed optical I/O applications|
    PCT/US2010/059852|WO2011081845A2|2009-12-31|2010-12-10|Integrated optical receiver architecture for high speed optical i/o applications|
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